Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

Author:

Tao Guoqiao,Scarpa Andrea,van Marwijk Leo,van Dijk Kitty,Kuper Fred

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference15 articles.

1. Snyder E. Introduction to predictive wafer level reliability. In: IRPS 2003 Tutorial Notes, Topic 112

2. Stress induced leakage current limiting to scale down EEPROM tunnel oxide thickness;Naruke;IEDM Tech. Dig.,1988

3. Yamada R-I, King T-J. Variable stress-induced leakage current and analysis of anomalous charge loss for flash memory application. In: 2003 IEEE IRPS Proceedings. p. 491–6

4. de Graaf C. et al. In: Non-Volatile Semiconductor Memory Workshop 1998. p. 101–4

5. Arai F, Maruyama T, Shirota R. Extended data retention process technology for highly reliable Flash EEPROMs of 106 to 107 W/E cycles. In: 1998 IEEE IRPS Proceedings. p. 378–82

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