Generation of a fault-tolerant clock through redundant crystal oscillators

Author:

Dür Wolfgang,Függer Matthias,Steininger Andreas

Funder

Intel Corp

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference21 articles.

1. J. H. Hong, D. J. Shin, Y. K. Jeong, and H. J. Park, “Clock fault monitoring circuit,” 1992, US Patent 5,479,420. [Online]. Available: http://www.google.com/patents/US5479420.

2. R. C. Bagley, “Method for detecting clock failure and switching to backup clock,” 1996, US Patent 5,828,243. [Online]. Available: http://www.google.com/patents/US5828243.

3. W. T. Ang, H. F. Rao, C. Yu, J. Liu, I.-C. Wey, A.-Y. Wu, H. Zhao, and J. Chen, “A clock-fault tolerant architecture and circuit for reliable nanoelectronics system,” in 2007 International Conference on Design Technology of Integrated Systems in Nanoscale Era, Sep. 2007, pp. 186–191.

4. H. Hui, Y. Changhong, C. Keming, and S. Lingling, “A novel clock-fault detection and self-recovery circuit based on time-to-voltage converter,” in 2008 International Conference on Communications, Circuits and Systems, May 2008, pp. 1204–1207.

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