A flexible soft error mitigation framework leveraging dynamic partial reconfiguration technology-Reference-Cited by-同舟云学术

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A flexible soft error mitigation framework leveraging dynamic partial reconfiguration technology

Published:2024-02 Issue: Volume:153 Page:115311
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Bai Jiyuan,Wang Xiang,Zhao Zifeng,Zhang Zikang,Cai Chang,Chen Gengsheng

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference35 articles.

1. D. Kobayashi, “Scaling trends of digital single-event effects: a survey of SEU and SET parameters and comparison with transistor performance,” in IEEE Trans. Nucl. Sci., vol. 68, no. 2, pp. 124–148, Feb. 2021, doi:https://doi.org/10.1109/TNS.2020.3044659.

2. Statistical reliability estimation of microprocessor-based systems;Savino;IEEE Trans. Comput.,2012

3. C. Cai et al., "Multiple layout-hardening comparison of SEU-mitigated filp-flops in 22-nm UTBB FD-SOI technology," in IEEE Trans. Nucl. Sci., vol. 67, no. 1, pp. 374–381, Jan. 2020, doi:https://doi.org/10.1109/TNS.2019.2956171.

4. Design and verification of multiple SEU mitigated circuits on SRAM-based FPGA system;Yu;Microelectron. Reliab.,2021

5. L. A. C. Benites et al., "Reliability calculation with respect to functional failures induced by radiation in TMR arm cortex-M0 soft-Core embedded into SRAM-based FPGA," in IEEE Trans. Nucl. Sci., vol. 66, no. 7, pp. 1433–1440, July 2019, doi:https://doi.org/10.1109/TNS.2019.2921796.

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