1. Cramming more components onto integrated circuits;Moore;Electronics,1965
2. TCAD investigation of a zero cost high voltage transistor architectures for logic memory circuits;Locati,2019
3. IEEE International Electron Devices Meeting;Brech,2003
4. Hot-carrier behaviour and Ron-BV trade-off optimization for p-channel LDMOS transistors in a 180 nm HV-CMOS technology;Park,2012
5. Optimized trench MOSFET technologies for power devices;Shenai;IEEE Transactions on electron devices,1992