Reliability study of 3D IC packaging based on through-silicon interposer (TSI) and silicon-less interconnection technology (SLIT) using finite element analysis

Author:

Che Fa XingORCID,Zhang Xiaowu,Lin Jong-Kai

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference26 articles.

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2. Current status of research and development for three-dimensional chip stack technology;Takahashi;Jpn. J. Appl. Phys.,2001

3. 3D packaging promises performance, reliability gains with small footprints and lower profiles;Karnezos;Chip Scale Rev.,2005

4. Total cost effective scallop free Si etching for 2.5D&3D TSV fabrication tehcnologies in 300mm wafer;Morikawa,2013

5. High aspect ratio TSV copper filling with different seed layers;Wolf,2008

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