Ultra wide voltage range consideration of reliability-aware STT magnetic flip-flop in 28 nm FDSOI technology

Author:

Cai H.,Wang Y.,Naviner L.A.B.,Zhao W.S.

Funder

French National Research Agency

IDEX Paris-Saclay

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference21 articles.

1. The emergence of spin electronics in data storage;Chappert;Nat. Mater.,2007

2. A magnetic tunnel junction based zero standby leakage current retention flip-flop;Ryu;IEEE Trans. VLSI,2012

3. Ultra low power magnetic flip-flop based on checkpointing/power gating and self-enable mechanisms;Chabi;IEEE Trans. CAS-I,2014

4. Design considerations and strategies for high-reliable STT-MRAM;Zhao;Microelectron. Reliab.,2011

5. A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write;Kazi,2013

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Breakdown Analysis of Magnetic Flip-Flop With 28-nm UTBB FDSOI Technology;IEEE Transactions on Device and Materials Reliability;2016-09

2. Low Power Magnetic Flip-Flop Optimization With FDSOI Technology Boost;IEEE Transactions on Magnetics;2016-08

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