Author:
Rajput Ravindra P.,Swamy M.N. Shanmukha
Reference22 articles.
1. Design and low-complexity implementation of matrix–vector multiplier for iterative methods in communication systems;Alshawi;IEEE Trans. VLSI Syst.,2015
2. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits;Chang;IEEE Trans. Circuits Syst.,2004
3. A 4.1ns compact 54×54-b multiplier utilising sign-select booth encoders;Goto;IEEE J. Solid State Circuit,1997
4. Design and implementation of a high-speed matrix multiplier based on word-width decomposition;Hong;IEEE Trans. VLSI Syst.,2006
5. Locally clocked pipelines and dynamic logic;Hoyer;IEEE Trans. VLSI Syst.,2001
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Performance Comparison Review of Multiplier Designs;2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2022-12-02
2. A survey paper on design and implementation of multipliers for digital system applications;Artificial Intelligence Review;2022-01-20
3. ATT: A Fault-Tolerant ReRAM Accelerator for Attention-based Neural Networks;2020 IEEE 38th International Conference on Computer Design (ICCD);2020-10