A novel high aspect ratio technology for MEMS fabrication using standard silicon wafers

Author:

Bertz Andreas,Küchler Matthias,Knöfler Roman,Gessner Thomas

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Metals and Alloys,Surfaces, Coatings and Films,Condensed Matter Physics,Instrumentation,Electronic, Optical and Magnetic Materials

Reference9 articles.

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2. H. Xie, G.K. Fedder, A CMOS z-axis capacitive accelerometer with comb-finger sensing, in: Proceedings of the 13th IEEE International Workshop on Micro Electro Mechanical Systems ‘MEMS 2000’, Miyazaki, Japan, January 23–27, 2000, pp. 26–32.

3. An RIE process for submicron silicon electromechanical structures;Zhang;J. Micromech. Microeng.,1992

4. U. Sridhar, et al., Single crystal silicon microstructures using trench isolation, in: Proceedings of the Conference on Transducers ’99, Sendai, Japan, June 7–10, 1999, Technical Digest, pp. 258–261.

5. M.A. Lemkin, T.N. Juneau, W.A. Clark, T.A. Roessig, T.J. Brosnihan, A low-noise digital accelerometer using integrated SOI-MEMS technology, in: Proceedings of the Conference on Transducers ’99, Sendai, Japan, June 7–10, 1999, Technical Digest, pp. 1294–1297.

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