System on Chip (SoC) Design and Test-Reference-Cited by-同舟云学术

System on Chip (SoC) Design and Test

Published:2019 Issue: Volume: Page:47-79
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Container-title:Hardware Security
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Author:

Bhunia Swarup,Tehranipoor Mark

Publisher

Elsevier

Reference40 articles.

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2. A tale of two designs: the cheapest and the most economic;Agrawal;Journal of Electronic Testing,1994

3. Economic effects in design and test;Dear;IEEE Design & Test of Computers,1991

4. J. Pittman, W. Bruce, Test logic economic considerations in a commercial VLSI chip environment, in: Proceedings of the 1984 International Test Conference on the Three Faces of Test: Design, Characterization, Production, IEEE Computer Society, pp. 31–39.

5. Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits;Bushnell,2004

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