1. Bounded model checking of software using SMT solvers instead of SAT solvers;Armando;Int. J. Softw. Tools Technol. Transf.,2009
2. A story about formal methods adoption by a railway signaling manufacturer;Bacherini,2006
3. A formal verification environment for railway signaling system design;Bernardeschi;Form. Methods Syst. Des.,1998
4. Symbolic model checking without BDDs;Biere,1999
5. Validation of interlocking systems by testing their models;Bonacchi,2014