Impact of local back biasing on performance in hybrid FDSOI/bulk high-k/metal gate low power (LP) technology

Author:

Fenouillet-Beranger C.,Perreau P.,Benoist T.,Richier C.,Haendler S.,Pradelle J.,Bustos J.,Brun P.,Tosti L.,Weber O.,Andrieu F.,Orlando B.,Pellissier-Tanon D.,Abbate F.,Richard C.,Beneyton R.,Gregoire M.,Ducote J.,Gouraud P.,Margain A.,Borowiak C.,Bianchini R.,Planes N.,Gourvest E.,Bourdelle K.K.,Nguyen B.Y.,Poiroux T.,Skotnicki T.,Faynot O.,Boeuf F.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference12 articles.

1. Fenouillet-Beranger C et al. Efficient Multi-VT FDSOI technology with UTBOX for low power circuit design. In: IEEE Symposium on VLSI technology; 2010. p. 65–6.

2. Impact of back bias on ultra-thin body and BOX (UTBB) devices;Liu;IEEE VSLI,2011

3. High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding;Weber;IEDM Tech Dig,2008

4. Fully-Depleted SOI Technology using high-k and single metal gate for 32nm node LSTP applications featuring 0.179μm2 6T-SRAM bitcell;Fenouillet-Beranger;IEDM Tech Dig,2007

5. FDSOI devices with thin BOX and ground plane integration for 32nm node and below;Fenouillet-Beranger;IEEE ESSDERC,2008

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