Scaling rules for SOI MOSFETs operating in the fully inverted mode-Reference-Cited by-同舟云学术

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Scaling rules for SOI MOSFETs operating in the fully inverted mode

Published:2004-10 Issue:10-11 Volume:48 Page:1943-1946
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Hanajiri T.,Niizato M.,Aoto K.,Toyabe T.,Nakajima Y.,Morikawa T.,Sugano T.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. Silicon-on-insulator technology: material to VLSI;Colinge,1991

2. Low-voltage SOI CMOS VLSI devices and circuits;Kuo,2001

3. Design of ion implanted MOSFETs with very small physical dimensions;Dennard;IEEE J. Solid-State Circuits,1974

4. Modeling of Cathodoluminescence and Photoluminescence Properties of Pulsed Laser-Deposited Europium-Activated Yttrium Oxide Thin Film Phosphors

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1. A Compact Analytical Model and Electrostatic Performance Investigation of Multilayer Groove Gate SOI-MOSFET;ICICCT 2019 – System Reliability, Quality Control, Safety, Maintenance and Management;2019-06-28

2. Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI MOSFETs—Part II: Model Derivation and Validity Confirmation;IEEE Transactions on Electron Devices;2014-09

3. Modeling of Drain Electric Flux Passing Through the BOX Layer in SoI MOSFETs—Part I: Preparation for Modeling Based on Conformal Mapping;IEEE Transactions on Electron Devices;2014-09

4. Quantitative Extraction of Electric Flux in the Buried-Oxide Layer and Investigation of Its Effects on MOSFET Characteristics;IEEE Transactions on Electron Devices;2013-12

5. Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications;IEEE Transactions on Electron Devices;2013-01

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