DC and low a frequency noise analysis of p channel gate all around vertically stacked silicon nanosheets
Author:
Publisher
Elsevier BV
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference16 articles.
1. https://irds.ieee.org/.
2. Low-frequency noise assessment of vertically stacked Si n-channel nanosheet FETs with different metal gates;Oliveira;IEEE Trans Electron Dev,2020
3. Low–frequency noise in vertically stacked Si n–channel nanosheet FETs;Oliveira;IEEE Electron Device Lett,2020
4. Analog figures of merit of vertically stacked silicon nanosheets nMOSFETs with two different metal gates for the sub-7 nm technology node operating at high temperatures;Silva;IEEE Trans Electron Dev,2021
5. Cretu B, Veloso A, Claeys C, Horiguchi N, Simoen E, “Low temperature investigation of n- channel GAA vertically stacked silicon nanosheets”, 2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS), 10.1109/EuroSOI- ULIS53016.2021.9560692.
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Is there a limit when the access resistance impact on the extraction of key GAA NS FETs devices parameters can (not) be avoided?;Solid-State Electronics;2023-11
2. In-depth static and low frequency noise assessment of p-channel gate-all-around vertically stacked silicon nanosheets;Solid-State Electronics;2023-03
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