Author:
Pham A.T.,Jungemann C.,Meinerzhagen B.
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference19 articles.
1. Thompson S, Anand N, Armstrong M, Auth C, Arcot B, Alavi M, et al. A 90nm logic technology featuring 50nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1μm2 SRAM cell. In: IEDM technical digest; 2002. p. 61–4.
2. Mistry K, Allen C, Auth C, Beattie B, Bergstrom D, Bost M, et al. A 45nm logic technology with high-k+metal gate transistors, strained Silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging. In: IEDM technical digest; 2007. p. 247–50.
3. Natarajan S, Armstrong M, Bost M, Brain R, Brazier M, Chang C-H, et al. A 32nm logic technology featuring 2nd-generation high-k+metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array. In: IEDM technical digest, 2008.
4. Piezoresistance effect in germanium and silicon;Smith;Phys Rev,1954
5. Mobility anisotropy and piezoresistance in silicon p-type inversion layers;Colman;J Appl Phys,1968
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