1. Kranti A, Chung T-M, Raskin J-P. Gate length scaling and microwave performance of double gate nano-transistors. In: International conference on nano science and technology (ICONSAT 2003), Hyatt Regency Kolkata, India, December 17–20, 2003. p. 88–9.
2. Silicon-on-insulator technology: materials to VLSI;Colinge,1997
3. Bonded planar double-metal-gate NMOS transistors down to 10nm;Vinet;IEEE Electron Device Lett,2005
4. Guarini KW, Solomon PM, Zhang Y, Chan KK, Jones EC, Cohen GM et al. Triple-self-aligned, planar double-gate MOSFETs: devices and circuits. In: Technical digest international electron devices meeting (IEDM), December 2001. p. 19.2.1–19.2.4.
5. Effect of interfacial SiO2 thickness for low temperature O2 plasma activated wafer bonding;Olbrechts;Microsyst Technol,2006