Pulse area dependent gradual resistance switching characteristics of CMOS compatible SiN x -based resistive memory

Author:

Kim Min-Hwi,Kim Sungjun,Bang Suhyun,Kim Tae-Hyeon,Lee Dong Keun,Cho Seongjae,Lee Jong-Ho,Park Byung-Gook

Funder

National Research Foundation of Korea

Korea government

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference34 articles.

1. Baek IG et al. Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses. IEEE IEDM Tech Dig; Dec. 2004. p. 587–90.

2. Nanoionics-based resistive switching memories;Waser;Nat Mater,2007

3. Fackenthal R et al. A 16Gb ReRAM with 200MB/s write and 1GB/s read in 27nm technology. ISSCC Dig Tech Papers; Feb. 2014. p. 338–40.

4. Liu T-Y et al. A 130.7mm2 2-layer 32Gb ReRAM memory device in 24nm technology. ISSCC Dig Tech Papers; Feb. 2013. p. 210–2.

5. Kawahara A et al. An 8Mb multi-layered cross-point ReRAM macro with 443MB/s write throughput. ISSCC Dig Tech Papers; Feb. 2012. p. 432–4.

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