Comprehensive investigation of the impact of lateral charge migration on retention performance of planar and 3D SONOS devices

Author:

Maconi A.,Arreghini A.,Monzio Compagnoni C.,Van den bosch G.,Spinelli A.S.,Van Houdt J.,Lacaita A.L.

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference24 articles.

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2. Highly manufacturable 32Gb Multi-Level NAND Flash memory with 0.0098μm2 cell size using TANOS (Si–Oxide–Al2O3–TaN) cell technology;Park;IEDM Tech Dig,2006

3. High performance SONOS memory cells free of drain turn-on and over-erase: compatibility issue with current flash technology;Cho;Electron Dev Lett,2000

4. Tanaka H, Kido M, Yahashi K, Oomura M, Katsumata R, Kito M, et al. Bit cost scalable technology with punch and plug process for ultra high density Flash memory. In: Symp VLSI Tech Dig; 2007. p. 14–5.

5. Jang J, Kim HS, Cho W, Cho H, Kim J, Shim S, et al. Vertical cell array using TCAT (terabit cell array transistor) technology for ultra high density NAND Flash memory. In: Symp VLSI Tech Dig; 2009. p. 192–3.

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