Study of threshold voltage extraction from room temperature down to 4.2 K on 28 nm FD-SOI CMOS technology

Author:

Berlingard Quentin,Lugo-Alvarez Jose,Bawedin Maryline,Contamin Lauriane,Galy Philippe,De Franceschi Silvano,Meunier Tristan,Vinet Maud,Gaillard Fred,Cassé Mikaël

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference21 articles.

1. J. Van Dijk et al., “Cryo-CMOS for Analog / Mixed-Signal Circuits and Systems,” 2020.

2. Cryo-CMOS Circuits and Systems for Quantum Computing Applications;Patra;IEEE J Solid-State Circuits,2018

3. Design and fabrication of cryogenic low noise amplifier in low RF band;Li;2007 Int Conf Microw Millim Wave Technol ICMMT,2007

4. H. O. Gulec, M. B. Yelten, “A cryogenic LC VCO utilizing cryogenic models of active devices,” In: Proc - 2019 6th Int Conf Electr Electron Eng ICEEE 2019, pp. 220–224, 2019, doi: 10.1109/ICEEE2019.2019.00049.

5. J. G. Fossum, V. P. Trivedi, Fundamentals of ultra–thin–body MOSFETs and finFETs, vol. 9781107030. 2011.

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Threshold voltage in FD-SOI MOSFETs;Solid-State Electronics;2024-07

2. Impact of Device Parametrics on a 10nm Gate Length SOI n-FinFET;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

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