Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications-Reference-Cited by-同舟云学术

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Evaluation of n-type gate-all-around vertically-stacked nanosheet FETs from 473 K down to 173 K for analog applications

Published:2023-10 Issue: Volume:208 Page:108729
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Silva V.C.P.^ORCID,Martino J.A.^ORCID,Simoen E.^ORCID,Veloso A.,Agopian P.G.D.^ORCID

Funder

Conselho Nacional de Desenvolvimento Científico e Tecnológico

Coordenação de Aperfeiçoamento de Pessoal de Nível Superior

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference15 articles.

1. Low Frequency noise assessment of vertically stacked Si n-channel nanosheet FETs with different metal gates;Oliveira;IEEE Trans Electron Dev,2020

2. High temperature influence on the trade-off between gm/I D and f T of nanosheet NMOS transistors with different metal gate stack;Silva,2021

3. Analog figures of merit of vertically stacked silicon nanosheets nMOSFETs with two different metal gates for the sub-7 nm technology node operating at high temperatures;Silva;IEEE Trans Electron Dev,2021

4. Low temperature investigation of n-channel GAA vertically stacked silicon nanosheets;Cretu,2021

5. Refined DC and Low-Frequency Noise Characterization at Room and Cryogenic Temperatures of Vertically Stacked Silicon Nanosheet FETs;Cretu;IEEE Trans Electron Dev,2023

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