1. Tri-gate fully-depleted CMOS transistors: fabrication, design and layout;Doyle;VLSI Technol Dig,2003
2. 5nm-Gate nanowire FinFET;Yang;VLSI Technol Dig,2004
3. High performance 5nm radius twin silicon nanowire MOSFET (TSNWFET): fabrication on bulk Si wafer, characteristics, and reliability;Suk;Tech Dig Int Electr Dev Meet,2005
4. Layout density analysis of FinFETs;Anil;Proc ESSDERC,2003
5. Novel 3D integration process for highly scalable nano-beam stacked-channels GAA (NBG) FinFETs with HfO2/TiN gate stack;Ernst;Tech Dig Int Electr Dev Meet,2006