PMOS junction optimization for 3D NAND FLASH memory with CMOS under array-Reference-Cited by-同舟云学术

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PMOS junction optimization for 3D NAND FLASH memory with CMOS under array

Published:2023-04 Issue: Volume:202 Page:108620
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Liao Jeng-Hwa,Ko Zong-Jie,Lin Hsing-Ju,Hsieh Jung-Yu,Yang Ling-Wu,Yang Tahone,Chen Kuang-Chao,Lu Chih-Yuan

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference12 articles.

1. A 128Gb 3b/cell NAND Flash Design Using 20nm Planar-Cell Technology;Naso;ISSCC Dig Tech Papers,2013

2. A 128Gb MLC NAND-Flash device using 16nm planar cell;Helm;ISSCC Dig Tech Papers,2014

3. Bit Cost Scalable technology with and plug process for ultra high density flash memory;Tanaka;VLSI Tech Symp Digest,2007

4. Jang J, Kim HS, Cho W, Cho H, Kim J, Shim SI, et al. Vertical Cell Array Using TCAT (Terabit Cell Array Transistor) Technology for Ultra High Density NAND Flash Memory. VLSI Tech Symp. Digest; 2009. pp. 192-193.

5. A 1-Tb Density 4b/Cell 3D-NAND Flash on 176-Tier Technology with 4-Independent Planes for Read using CMOS-Under-the-Array;Pekny;ISSCC,2022

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