Influence of carrier velocity related parameters on the propagation delay time of inverters with high-k gate dielectric CMISFETs
Author:
Publisher
Elsevier BV
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference20 articles.
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3. Goto K, Sambonsugi Y, Sugii T. Co salicide compatible 2-step activation annealing process for deca-nano scaled MOSFETs. In: Technical Digest of 1999 Symposium on VLSI Technology. p. 49–50
4. Caillat C, Deleonibus S, Guegan G, Tedesco S, Dal’zotto B, Heitzmann M, et al. 65 nm physical gate length NMOFSETs with heavy ion implanted pockets and highly reliable 2nm-thick gate oxide for 1.5 V operation. In: Technical Digest of 1999 Symposium on VLSI Technology. p. 89–90
5. 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays;Chau;IEDM Tech. Dig.,2000
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