Parasitic capacitance removal of sub-100nm p-MOSFETs using capacitance–voltage measurements-Reference-Cited by-同舟云学术

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Parasitic capacitance removal of sub-100nm p-MOSFETs using capacitance–voltage measurements

Published:2012-02 Issue: Volume:68 Page:51-55
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Steinke Daniel R.,Piccirillo Joseph,Gausepohl Steven C.,Vivekand Saikumar,Rodgers Martin P.,Lee Ji Ung

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference10 articles.

1. A new 'shift and ratio' method for MOSFET channel-length extraction

2. New ratio method for effective channel length and threshold voltage extraction in MOS transistors

3. Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET's

4. An accurate gate length extraction method for sub-quarter micron MOSFET's

5. A new approach to determine the effective channel length and the drain-and-source series resistance of miniaturized MOSFET's

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Numerical simulation of analog metrics and parasitic capacitances of GaAs GS-GAA FinFET for ULSI switching applications;The European Physical Journal Plus;2022-01

2. Investigation of parasitic capacitances of In2O5Sn gate electrode recessed channel MOSFET for ULSI switching applications;Microsystem Technologies;2017-03-07

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