Wafer level packaging of a tape flip-chip chip scale packages-Reference-Cited by-同舟云学术

Wafer level packaging of a tape flip-chip chip scale packages

Published:2001-05 Issue:5 Volume:41 Page:705-713
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Hotchkiss Greg,Amador Gonzalo,Edwards Darvin,Hundt Paul,Stark Les,Stierman Roger,Heinen Gail

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference13 articles.

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4. Akiyama Y, Nishimura A, Anjoh I. Chip scale packaging for memory devices. Proceedings of the 1998 Electronic Components and Technology Conference (ECTC), Seattle, WA. p. 477–81

5. Windsor C, Pienimaa S, Chung T. Chip scale packaging technologies. Proceedings of the Technical Program. NEPCON West '96 Conference. vol. 2. p. 1005–12

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