A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparators
Author:
Funder
Research Grants Council, University Grants Committee
Publisher
Elsevier BV
Reference18 articles.
1. A 2.2 mW 1.75 GS/s 5 bit folding flash ADC m digital CMOS;Verbruggen;IEEE J. Solid State Circ.,2009
2. A 5-bit 3.2-GS/s flash ADC with a digital offset calibration scheme;Lin;IEEE Trans. Very Large Scale Integr. Syst.,2010
3. A 7.8-mW 5-b 5-GS/s dual-edges-triggered time-based flash adc;Chan;IEEE Trans. Circ. Syst. I Reg. Papers,2017
4. Extra bit generation for high-speed time-based flash ADCs in 65 nm CMOS;Nasrollahpour,2018
5. A 65-nm cmos 6-bit 2.5-GS/s 7.5-mW 8X time-domain interpolating flash ADC with sequential slope-matching offset calibration;Oh;IEEE J. Solid State Circ.,2019
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