A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic-Reference-Cited by-同舟云学术

A high-performance VLSI architecture for reconfigurable FIR using distributed arithmetic

Published:2016-06 Issue: Volume:54 Page:37-46
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Mohanty Basant Kumar,Meher Pramod Kumar,Singhal Subodh Kumar,Swamy M.N.S.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference22 articles.

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4. T. Solla, R. Makela, M. Liljeroos, O. Vainio, Application-specific filter processor for flexible receivers, in: Proceedings of 19th NORCHIP Conference on Kista, Sweden, Novemver 2001, pp. 53–58.

5. T. Solla, O. Vainio, Comparison of programmable FIR filter architectures for low power, in: Proceedings of 28th European Solid-State Circuits Conference on Firenze, Italy, September 2002, pp. 759–762.

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