Hybrid asynchronous circuit generation amenable to conventional EDA flow-Reference-Cited by-同舟云学术

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Hybrid asynchronous circuit generation amenable to conventional EDA flow

Published:2019-01 Issue: Volume:64 Page:29-39
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Park Heechun,Kim Taewhan

Funder

National Research Foundation of Korea (NRF)

Korea Government (Ministry of Science and ICT)

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference30 articles.

1. Low Power Methodology Manual: for System-on-chip Design;Keating,2007

2. Low Power Design Essentials;Rabaey,2009

3. Giving Technology 2020 Vision;Frantz,2008

4. GALS System Design: Side Channel Attack Secure Cryptographic Accelerators;Gürkaynak,2006

5. An automatic design flow for implementation of side channel attacks resistent crypto-chips;Ghavami,2007

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