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A novel systolic array processor with dynamic dataflows

  • Published:2022-07 Issue: Volume:85 Page:42-47
  • ISSN:0167-9260
  • Container-title:Integration
  • language:en
  • Short-container-title:Integration

Author:

Wang Bo,Ma ShengORCID,Zhu Guoyi,Yi Xiao,Xu Rui

Funder

National Key Research and Development Program of China

National Natural Science Foundation of China

Natural Science Foundation of Hunan Province

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference14 articles.

1. In-datacenter performance analysis of a tensor processing unit;Jouppi,2017

2. Mapping signal processing algorithms into the systolic arrays;Snopce,2020

3. A novel unified method for the fast computation of discrete image moments on grayscale images;Hua;J. Real-Time Image Process.,2020

4. Sparse-TPU: adapting systolic arrays for sparse matrices;He,2020

5. A systolic array based GTD processor with a parallel algorithm;Yang;IEEE Trans. Circ. Syst. I: Reg. Pap.,2015

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1. EWS: An Energy-Efficient CNN Accelerator With Enhanced Weight Stationary Dataflow;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-07

2. SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow;ACM Transactions on Design Automation of Electronic Systems;2024-01-15

3. Optimization and analysis of FPGA-based systolic array for matrix multiplication;AIP Conference Proceedings;2024

4. FPGA Implementation of Cycle-Reduced Diagonal Data Flow Systolic Array for Edge Device AI;2023 20th International SoC Design Conference (ISOCC);2023-10-25

5. Domain-Specific Architectures: Research Problems and Promising Approaches;ACM Transactions on Embedded Computing Systems;2023-01-24
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