Statistical analysis of large on-chip power grid networks by variational reduction scheme-Reference-Cited by-同舟云学术

Statistical analysis of large on-chip power grid networks by variational reduction scheme

Published:2010-04 Issue:2 Volume:43 Page:167-175
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Li Duo,Tan Sheldon X.-D.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference34 articles.

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5. S. Nassif, Delay variability: sources, impact and trends, in: Proceedings of the IEEE International Solid-State Circuits Conference, San Francisco, CA, 2000, pp. 368–369.

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