Data-path aware high-level ECO synthesis-Reference-Cited by-同舟云学术

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Data-path aware high-level ECO synthesis

Published:2019-03 Issue: Volume:65 Page:88-96
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Shiroei Masoud,Alizadeh Bijan^ORCID,Fujita Masahiro

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference28 articles.

1. Redundant-wires-aware ECO timing and mask cost optimization;Fang,2010

2. TRECO: dynamic technology remapping for timing engineering change orders;Ho;IEEE Trans. Comput. Aided Des. Integrated Circ. Syst.,2012

3. ECO-Map: technology remapping for post-mask ECO using simulated annealing;Modi,2008

4. Reap what you sow: spare cells for post-silicon metal fix;Chang,2008

5. Minimal logic re-synthesis for engineering change;Swamy,1997

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