1. Y. Kretchmer, Using multi-bit register inference to save area and power: the good, the bad, and the ugly, EE Times Asia, May 2001.
2. J.-T. Yan, Z.-W. Chen, Construction of constrained multi-bit flip-flops for clock power reduction, in: Proceedings of IEEE International Conference on Green Circuits and Systems, 2010, pp. 675–678.
3. Y.-T. Chang, C.-C. Hsu, M.P.-H. Lin, Y.-W. Tsai, S.-F. Chen, Post-placement power optimization with multi-bit flip-flops, in: Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp. 218–223, 2008.
4. INTEGRA: Fast multi-bit flip-flop clustering for clock power saving;Jiang;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,2012
5. Power-driven flip-flop merging and relocation;Wang;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,2012