Formal verification of high-level data-flow synthesis designs using relational modeling and symbolic computation
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference26 articles.
1. A. Peymandoust, G.D. Micheli, Using symbolic algebra in algorithmic level DSP synthesis, in: Proceedings of the Design Automation Conference, 2001, pp. 277–282.
2. A. Peymandoust, G.D. Micheli, Symbolic algebra and timing driven data-flow synthesis, in: Proceedings of the International Conference on Computer-Aided Design, 2001, pp. 300–305.
3. Application of symbolic computer algebra in high-level data-flow synthesis;Peymandoust;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2003
4. M. Ciesielski, S. Askar, D. Gomez-Prado, J. Guillot, E. Boutillon, Data-flow transformations using Taylor expansion diagrams, in: Proceedings of the Conference on Design Automation and Test in Europe, 2007, pp. 455–460.
5. M. Ciesielski, P. Kalla, Z. Zeng, B. Rouzeyre, Taylor expansion diagrams: a compact, canonical representation with applications to symbolic verification, in: Proceedings of the Conference on Design, Automation and Test in Europe, 2002, pp. 285–289.
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