Improved predictability, timing yield and power consumption using hierarchical highways-on-chip planning methodology

Author:

Jahanian A.,Saheb Zamani M.,Safizadeh H.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference26 articles.

1. P. Dasgupta, Revisiting VLSI interconnects in deep sub-micron: some open questions, in: Proceedings of the International Conference on VLSI Design, 2005, pp. 615–620.

2. H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, N. Sherwani, Integrated floorplanning and interconnect planning, in: Proceedings of the International Conference on Computer Aided Design, 1999, pp. 354–357.

3. DUNE—a multilayer gridless routing system;Cong;IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems,2001

4. Wire width planning for interconnect performance optimization;Cong;IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems,2002

5. H. Xiang, I.M. Liu, D.F. Wong, Wire planning with bounded over-the-block wires, in: Sixth International Symposium on Quality of Electronic Design, 2005, pp. 622–627.

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