The study of TSV-induced and strained silicon-enhanced stress in 3D-ICs

Author:

Zhou JindongORCID,Chen YuyangORCID,Jing YouliangORCID,Zhou Pingqiang

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference22 articles.

1. K. Saban, Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency, Xilinx, White Paper, WP380, Vol. 1, (1) 2011, pp. 1–10.

2. A 1.33-Tb 4-bit/cell 3-D flash memory on a 96-Word-Line-Layer technology;Shibata;IEEE J. Solid-State Circuits (JSSC),2019

3. 30.1 A 176-stacked 512Gb 3b/cell 3D-NAND flash with 10.8Gb/mm2 density with a peripheral circuit under cell array architecture;Park,2021

4. Stress-aware performance evaluation of 3D-stacked wide I/O DRAMs;Li,2017

5. TSV stress-aware full-chip mechanical reliability analysis and optimization for 3-d IC;Jung;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. (TCAD),2012

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Fine-Pitch $30\ \mu \mathrm{m}$ Cu-Cu Bonding using Electroless Nano-Ag;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05

2. Process Optimization and Performance Evaluation of TSV Arrays for High Voltage Application;Micromachines;2022-12-30

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