Timing modeling of latch-controlled sub-systems-Reference-Cited by-同舟云学术

Timing modeling of latch-controlled sub-systems

Published:2007-02 Issue:2 Volume:40 Page:62-73
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Do Kyung Tae,Kim Young Hwan,Son Haeng Seon

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference23 articles.

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4. C. Yun, X. Wei, L. Ping, Hierarchical Hard IP Reuse in SOC, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions, vol. 2, New York, USA, July 2002, pp. 1449–1453.

5. H. Qi, Z. Jiang, J. Wei, IP reusable design methodology, in: Proceedings of Fourth International Conference on ASIC, Shanghai, China, October 2001, pp. 756–759.

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