APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement-Reference-Cited by-同舟云学术

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APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement

Published:2007-07 Issue:4 Volume:40 Page:406-419
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Wei Yaoguang,Dong Sheqin,Hong Xianlong

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference20 articles.

1. A.E. Caldwell, A.B. Kahng, S. Mantik, I.L. Markov, A. Zelikovsky, On wirelength estimations for row-based placement, in: Proceedings ISPD, April 1998, pp. 4–11.

2. H. Chen, C.K. Cheng, A.B. Kahng, I. Mandoiu, Q. Wang., Estimation of wirelength reduction for λ-geometry vs. Manhattan placement and routing, in: Proceedings of ACM/IEEE Workshop System Level Interconnect Prediction, 2003, pp. 71–76.

3. H. Chen, C.K. Cheng, A.B. Kahng, I.I. Mandoiu, Q. Wang, B. Yao. The Y architecture for on-chip interconnect: analysis and methodology, IEEE Trans. Comput.-Aided Des. Integrated Circuits Syst. (2005) 588–599.

4. H. Chen, B. Yao, F. Zhou, C.-K. Cheng, The Y-architecture: yet another on-chip interconnect solution, in: Proceedings of the ASP-DAC 2003, January 2003, pp. 840–846.

5. C. Chu, Y.C. Wong, Fast and accurate rectilinear Steiner minimal tree algorithm for VLSI design, in: Proceedings of ISPD, 2005, pp. 28–35.

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1. Geometry Independent Wirelength Estimation Method in VLSI Routing;2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems;2013-01

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