1. The design of an all-digital phase-locked loop with small DCO hardware and fast phase lock;Chiang;IEEE Trans. Circuits Syst. II: Analog Digital Signal Process.,1999
2. M. Saint-Laurent, G.P. Muyshondt, A digitally controlled oscillator constructed using adjustable resistors, in: Proceedings of IEEE Southwest Symposium on Mixed-Signal Design, 2001, pp. 80–82.
3. Phase-domain all-digital phase-locked loop;Staszewski;IEEE Trans. Circuits Systems II,2005
4. P. Raha, S. Randall, R. Jennings, B. Helmick, A. Amerasekera, B. Haroun, A robust digital delay line architecture in a 0.13μm CMOS technology node for reduced design and process sensitivities, in: Proceedings of the International Symposium on Quality Electronic Design (ISQED ‘02), 2002, pp. 148–153.
5. Hiroyoshi Tomita, Delay Circuit Having a Capacitor and Having Reduced Power Supply Voltage Dependency, US Patent 7, 352, 223 B2, April 1, 2008.