Block flipping and white space distribution for wirelength minimization-Reference-Cited by-同舟云学术

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Block flipping and white space distribution for wirelength minimization

Published:2009-02 Issue:2 Volume:42 Page:246-253
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Sham Chiu-Wing,Young Evangeline F.Y.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference17 articles.

1. H. Murata, K. Fujiyoshi, S. Nakatake, Y. Kajitani, VLSI module placement based on rectangle-packing by the sequence-pair, IEEE Trans. Comput. Aided Des. Integrated Circuit Syst. (1996) 1518–1524.

2. Y.C. Chang, Y.W. Chang, G.M. Wu, S.W. Wu, B*-trees: a new representation for non-slicing floorplans, in: Proceedings of the 37th ACM/IEEE Design Automation Conference, 2000, pp. 458–463.

3. X.P. Tang, R.Q. Tian, D.F. Wong, Fast evaluation of sequence pair in block placement by longest common subsequence computation, in: Proceedings of Design, Automation and Test in Europe Conference and Exhibition, 2000, pp. 106–111.

4. J.M. Lin, Y.W. Chang, Tcg: a transitive closure graph-based representation for non-slicing floorplans, in: Proceedings of the 38th ACM/IEEE Design Automation Conference, 2001, pp. 764–769.

5. S.N. Adya, I.L. Markov, Fixed-outline floorplanning: enabling hierarchical design, in: Proceedings of International Conference on Computer Design, 2003, pp. 1120–1135.

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1. Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2022

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