Author:
Condo Carlo,Martina Maurizio,Ruo Roch Massimo,Masera Guido
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference47 articles.
1. P. Guerrier, A. Greiner, A generic architecture for on-chip packet-switched interconnections, in: Design, Automation and Test in Europe Conference and Exhibition, 2000, pp. 250–256.
2. W.J. Dally, B. Towels, Route packets, not wires: on-chip interconnection networks, in: Design Automation Conference, 2001, pp. 684–689.
3. S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani, A network on chip architecture and design methodology, in: IEEE Computer Society Annual Symposium on VLSI, 2002, pp. 105–112.
4. Networks on chips;Benini;IEEE Comput.,2002
5. S.V. Tota, M.R. Casu, M.R. Roch, L. Rostagno, M. Zamboni MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture, in: Design, Automation and Test in Europe Conference and Exhibition, 2010, pp. 45–50.