Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning-Reference-Cited by-同舟云学术

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Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning

Published:2017-09 Issue: Volume:59 Page:98-108
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Schmidt Bernhard,Ziener Daniel,Teich Jürgen,Zöllner Christian

Funder

Bavarian Ministry of Economic Affairs

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference42 articles.

1. Xilinx Inc., 7 Series FPGAs Overview, 2012.

2. D. Koch, J. Torresen, Advances and Trends in Dynamic Partial Run-time Reconfiguration, in: Dagstuhl 10281: Dynamically Reconfigurable Architectures, Schloss Dagstuhl, Germany, 2010, p. 6.

3. Xilinx Inc., Device Reliability Report: Second Quarter 2013, Tech. rep., Xilinx Inc., 2013.

4. C. Carmichael, M. Caffrey, A. Salazar, Correcting Single-Event Upsets Through Virtex Partial Configuration. Xilinx Corp., Tech. Rep., XAPP216 (v1.0), Tech. rep., Xilinx Inc., 2000.

5. Seu-induced persistent error propagation in fpgas;Morgan;IEEE Trans. Nucl. Sci.,2005

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