A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link

Author:

Kumar Mithilesh,Majumder Alak,Mondal Abir J.,Raychowdhury Arijit,Bhattacharyya Bidyut K.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference26 articles.

1. A low-power SerDes for high-speed on chip networks;Park,2017

2. A 40Gbps quarter rate SerDes transmitter and receiver chipset in 65nm CMOS;Zheng;IEEE J. Solid State Circ.,2017

3. Design and analysis of RF/high-speed SerDes in 28nm CMOS technology for aerospace applications;Cosimi,2020

4. A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE;Neyestanak;IEEE J. Solid State Circ.,2007

5. Low power CMOS digital design;Chandrakasan;IEEE J. Solid State Circ.,1992

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线,采集、加工和组织学术论文而形成的新型学术文献查询和分析系统,可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容,当前同舟云学术共收录了国内外主流学术期刊6万余种,收集的期刊论文及会议论文总量共计约1.5亿篇,并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询!咨询电话:010-8811{复制后删除}0370

www.globalauthorid.com

TOP

Copyright © 2019-2024 北京同舟云网络信息技术有限公司
京公网安备11010802033243号  京ICP备18003416号-3