Design of robust analog integrated circuit based on process corner performance variability minimization

Author:

Rout Prakash KumarORCID,Acharya Debiprasad Priyabrata,Nayak Debasish,Nanda Umakanta

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference18 articles.

1. CMOS Digital Integrated Circuits Analysis and Design;Kang,2003

2. An assigned probability technique to derive realistic worst case timing models of digital standard cells;Dal Fabbro,1995

3. Impact of unrealistic worst case modeling on the performance of VLSI circuits on deep submicron CMOS technologies;Nardi;IEEE Trans. Semicond. Manuf.,1999

4. Realistic worst-case spice file extraction using BSIM3;Chen,1995

5. Realistic statistical worst-case simulations of VLSI circuits;Bolt;IEEE Trans. Semicond. Manuf.,1991

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