Statistical modeling and analysis of chip-level leakage power by spectral stochastic method

Author:

Shen Ruijing,Tan Sheldon X.-D.,Mi Ning,Cai Yici

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference34 articles.

1. H. Chang, S.S. Sapatnekar, Full-chip analysis of leakage power under process variations, including spatial correlations, in: Proceedings of Design Automation Conference (DAC), ACM, New York, NY, USA, 2005, pp. 523–528.

2. R. Shen, N. Mi, S.X.-D. Tan, Y. Cai, X. Hong, Statistical modeling and analysis of chip-level leakage power by spectral stochastic method, in: Proceedings of Asia South Pacific Design Automation Conference (ASPDAC), 2009, pp. 161–166.

3. S. Nassif, Delay variability: sources, impact and trends, in: Proceedings of IEEE International Solid-State Circuits Conference, San Francisco, CA, 2000, pp. 368–369.

4. Semiconductor Industry Association, International technology roadmap for semiconductors, 2006 〈http://www.itrs.net/Links/2006Update/2006UpdateFinal.htm〉.

5. V. De, S. Borkar, Technology and design challenges for low power and high performance, in: Proceedings of International Symposium on Low Power Electronics and Design (ISLPED), 1999, pp. 163–168.

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