Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation-Reference-Cited by-同舟云学术

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Loop aware CFG matching strategy for accurate performance estimation in IR-level native simulation

Published:2019-03 Issue: Volume:65 Page:444-454
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Matoussi Omayma,Pétrot Frédéric

Funder

BPI France

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference30 articles.

1. Using abstract cpu subsystem simulation model for high level hw/sw architecture exploration;Bouchhima,2005

2. Automatic instrumentation of embedded software for high level hardware/software co-simulation;Bouchhima,2009

3. Fast and accurate timed execution of high level embedded software using hw/sw interface simulation model;Bouchhima,2004

4. High-level loop optimizations for gcc;Berlin,2004

5. Graph-based comparison of executable objects;Dullien,2005

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