Verification and revision of the power-down mode for hierarchical analog circuits-Reference-Cited by-同舟云学术

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Verification and revision of the power-down mode for hierarchical analog circuits

Published:2020-07 Issue: Volume:73 Page:1-9
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Neuner Maximilian,Graeb Helmut

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference18 articles.

1. Analog power-down synthesis;Zwerger;IEEE Trans. Comput. Aided Des. Integrated Circ. Syst.,2017

2. Transistor aging-induced degradation of analog circuits: impact analysis and design guidelines;Maricau,2011

3. Mismatch drift: a reliability issue for analog MOS circuits;Michael,1992

4. Stress-induced MOSFET mismatch for analog circuits;Chen,2001

5. Detection of asymmetric aging-critical voltage conditions in analog power-down mode;Zwerger,2015

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04

2. Analysis of Negative Feedback Stability of Operational Amplifiers and Research on Application Validation Methods;2022 IEEE 5th International Conference on Automation, Electronics and Electrical Engineering (AUTEEE);2022-11-18

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