Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries-Reference-Cited by-同舟云学术

Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Published:2006-07 Issue:4 Volume:39 Page:382-406
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Shaw Donald,Al-Khalili Dhamin,Rozon Come

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference48 articles.

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4. Simulated fault injection: a methodology to evaluate fault tolerant microprocessor architectures;Choi;IEEE Trans. Reliab.,1990

5. J. Coppens, Logical fault analysis of fault secure systems using VHDL. M. Eng. Thesis, Department of Electrical and Computer Engineering, Royal Military College of Canada, 1997.

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