Reducing test application time, test data volume and test power through Virtual Chain Partition

Author:

Solana José M.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference34 articles.

1. A. Al-Yamani, E. Chmelar, M. Grinchuk, Segmented addressable scan architecture, in: Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), May 2005, pp. 405–411.

2. Austria Microsystems, 0.35 CMOS core cells datasheets 〈http://asic.austriamicrosystems.com/databooks/index_c35.html〉.

3. S. Banerjee, D.R. Chowdhury, B.B. Bhattacharya, An efficient scan tree design for compact test pattern set, in: Proceedings of the 19th International Conference on VLSI Design, January 2006, pp. 175–180.

4. Space compactor design in VLSI circuits based on graph theoretic concepts;Biswas;IEEE Trans. Instrum. Meas.,2006

5. Y. Bonhomme, T. Yoneda, H. Fujiwara, P. Girard, An efficient scan tree design for test time reduction, in: Proceedings of the 9th IEEE European Test Symposium (ETS’04), May 2004, pp. 174–179.

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1. Test Pattern Reduction Using Various ML Algorithms;2023 IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER);2023-10-13

2. Balanced Scan Chain Analysis to Improve Fault Coverage in VLSI circuits;2021 6th International Conference on Inventive Computation Technologies (ICICT);2021-01-20

3. Two-stage low power test data compression for digital VLSI circuits;Computers & Electrical Engineering;2018-10

4. IPRM: IP core resource multiplexing of core wrapper design for reducing test application time in DVFS-based multicore SoCs;Integration;2017-03

5. Enhancement of test data compression with multistage encoding;Integration;2014-09

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