Efficient design of decimation filter using linear programming and its FPGA implementation

Author:

Aggarwal SupriyaORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference17 articles.

1. An economical class of digital filters for decimation and interpolation;Hogenauer;IEEE Trans. Acoust. Speech Signal Process.,1981

2. Sharpening the response of a symmetric nonrecursive filter by multiple use of the same filter;Kaiser;IEEE Trans. Acoust. Speech Signal Process.,1977

3. Application of filter sharpening to cascaded integrator-comb decimation filters;Kwentus;IEEE Trans. Signal Process.,1997

4. A new two-stage sharpened comb decimator;Jovanovic-Dolecek;IEEE Trans. Circ. Syst. I: Regul. Pap.,2005

5. High-speed sharpening of decimating cic filter;Stephen;Electron. Lett.,2004

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1. A Brief Review on Hardware Efficient Cascaded Integrator Comb Filters;2023 International Conference on Sustainable Communication Networks and Application (ICSCNA);2023-11-15

2. APOS is Not Enough: Towards a More Appropriate Way to Estimate Computational Complexity in CIC Decimation Architectures;Communications in Computer and Information Science;2023

3. Low Power Implementation of Compensated and Sharpened CIC Decimation Filter;2022 IEEE 9th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON);2022-12-02

4. Hardware-Efficient Decimation with Spectral Shape Approximating the Nth Power of a Dirichlet Kernel;Circuits, Systems, and Signal Processing;2022-03-31

5. Real-Time FPGA Implementation of FIR Filter Using OpenCL Design;Journal of Signal Processing Systems;2022-01

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