Author:
Asif Shahzad,Vesterbacka Mark
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Reference23 articles.
1. Power-delay product minimization in high-performance 64-bit carry-select adders;Neve;IEEE Transactions on Very Large Scale Integration (VLSI) Systems,2004
2. M. Alioto, G. Palumbo, M. Poli, A gate-level strategy to design carry select adders, in: Proceedings of the International Symposium on Circuits and Systems, vol. 2, May 2004, pp. 465–468.
3. Digital Integrated Circuits: A Design Perspective;Rabaey,2003
4. Integrated Circuit Design;Weste,2010
5. Yan Sun, Xin Zhang, Xi Jin, High-performance carry select adder using fast all-one finding logic, in: Proceedings of the Second Asia International Conference on Modeling and Simulation, May 2008, pp. 1012–1014.
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. An Energy-Efficient Quaternary Serial Adder for Nanoelectronics;2018 IEEE 48th International Symposium on Multiple-Valued Logic (ISMVL);2018-05
2. Performance Analysis of 1 Bit Full Adder Circuits for 45 nm Technology;Journal of Nanoelectronics and Optoelectronics;2018-01-01
3. Design and analysis of carbon nanotube FET based quaternary full adders;Frontiers of Information Technology & Electronic Engineering;2016-10