Digital-domain chopping technique for high-resolution PLL-based sensor interfaces-Reference-Cited by-同舟云学术

Digital-domain chopping technique for high-resolution PLL-based sensor interfaces

Published:2016-10 Issue: Volume:249 Page:294-302
ISSN:0924-4247
Container-title:Sensors and Actuators A: Physical
language:en
Short-container-title:Sensors and Actuators A: Physical

Author:

Marin Jorge,Van Rethy Jelle,Vergauwen Johan,Gielen Georges

Funder

Melexis

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Metals and Alloys,Surfaces, Coatings and Films,Condensed Matter Physics,Instrumentation,Electronic, Optical and Magnetic Materials

Reference24 articles.

1. A 20-b ±40-mV range;Wu;IEEE J. Solid-State Circuits,2012

2. A high-linearity capacitance-to-digital converter suppressing charge errors from bottom-plate switches;Li;IEEE Trans. Circuits Syst. I: Regul. Pap.,2014

3. A capacitance-to-digital converter for displacement sensing with 17b resolution and 20μs conversion time;Xia,2012

4. A 0.5V, 11.3-μw, 1-kS/s resistive sensor interface circuit with correlated double sampling;Ha,2012

5. An integrated energy-efficient capacitive sensor digital interface circuit;Omran;Sens. Actuators A: Phys.,2014

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